Semiconductor memory devices may be classified into volatile memory devices and nonvolatile memory devices. In contrast to volatile memory devices, nonvolatile memory devices, such as Flash memory devices, retain stored data even when power is removed. Therefore, nonvolatile memory devices, such as Flash memory devices, are widely used in memory cards and in electronic devices. Due to rapidly growing digital information technology, there are demands to continuingly increase the memory density of the Flash memory devices while maintaining, if not reducing, the size of the devices.
Three-dimensional (3D)-NAND Flash memory devices have been investigated for increasing the memory density. The 3D-NAND architecture includes a stack of memory cells having charge storage structures (e.g., floating gates, charge traps or the like), a stack of alternating control gates and dielectric materials, and charge blocking materials disposed between the charge storage structures and the adjacent control gates. An oxide material, such as silicon oxide, is conventionally used as the dielectric material. The charge blocking material may be an inter-poly dielectric (IPD) material, such as oxide-nitride-oxide (ONO) material.
FIG. 1 shows a semiconductor structure 100 that may be further processed to form a 3D-NAND Flash memory device. The semiconductor structure 100 includes a stack 110 of alternating tier control gates 108 and tier dielectric materials 105 over a material 103 to be used as a control gate of a select device, such as a select gate source (SGS) or a select gate drain (SGD), floating gates 400, charge blocking material (411, 412, 413) positioned between the floating gates 400 and adjacent tier control gates 108, and a channel material 600 extending through the stack 110, the select gate material 103, a source oxide material 102, and a portion of a source 101. The semiconductor structure 100 may further include a tunnel oxide material 580 between the floating gates 400 and the channel material 600. The source 101 could be formed in and/or on a substrate, such as a semiconductor substrate comprising monocrystalline silicon. Optionally, the semiconductor structure 100 may include an etch stop material 104 (as shown in FIG. 1). The control gates 108 each has a height of Ht. The floating gates 400 each has a height of H2. Due to the presence of the charge blocking material (411, 412, 413) around the discrete floating gate 400, the height H2 of each discrete floating gate 400 is less than the height H1 of an adjacent tier control gate 108. In addition, the floating gate 400 is not aligned with the adjacent tier control gate 108.
During use and operation, charge may get trapped on a charge trapping portion of the charge blocking material (e.g., nitride portions 412 of the charge blocking material (412, 413)) that are horizontally disposed between a floating gate (400) and adjacent tier dielectric material (105), but not vertically disposed between the floating gates (400) and adjacent tier control gates (108). Trapped charge can migrate along the charge blocking material (412, 413), such as through program, erase or temperature cycling. The presence of the charge blocking material (412, 413) creates a direct path for programming/erasing into the charge trapping portion of the charge blocking material (e.g., the nitride portions 412 of the charge blocking material (412, 413)) and degrades cell program-erase cycling. Such charge trapping or movement can alter the threshold voltage (Vt) of the memory cells or degrade incremental step pulse programming (ISPP) relative to memory cells that do not have such charge trapping in the nitride. Charge trap jeopardizes the controllability of the channel characteristics and the reliability of the 3D-NAND Flash memory device. Therefore, it would be beneficial to minimize charge trap in the horizontal ONO charge blocking material portions.